There are many predictions that Moore’s Law is likely to hit a wall sooner rather than later, but how soon is open for debate. There are technologies that promise continuous increases in performance that do not depend on doubling the transistor density, and the timing of all of that will have far-reaching implications. At last week’s TSMC Technology Symposium 2021, TSMC CEO CC Wei set the example of data centers, which consume more than one percent of the global electricity generated.
TSMC has no plans beyond 2 nm
“Estimates suggest that global data center electricity use is projected to grow five to 40 times between 2010 and 2030. Why do projections vary so much?” – Wei asked. “The divergent estimates are due in part to the difficulty of making an accurate projection of our footprint. There are too many variables to consider, even if Moore’s Law can continue. ‘
The pessimistic projections are based on the assumption that Moore’s Law is coming to an end, and the efficiency improvements delivered by semiconductor process technologies can no longer keep up with the demand for data and computing power, he notes. the CEO of TSMC.
As TSMC’s silicon downsizing roadmap appears to end at the 2nm node; The world’s largest semiconductor foundry is turning to a combination of packaging technologies and the use of new materials to stay on track to increase transistor density to boost performance and reduce energy demand.
“We have a predictable and reliable roadmap for both 2D scaling and 3D ICs to pursue Moore’s Law and beyond.”Wei said. “We continue to offer the most advanced logic technology to show that 2D scaling is alive and well.”
The company said that at this time, there is no plan to process nodes beyond 2 nm. At the technology symposium, TSMC provided some details on the company’s first 2nm factory, to be built in Hsinchu, Taiwan. In addition to providing details on where it will be built, the company did not elaborate on a time frame for production or capacity.
The change of technology
At the moment, the change in process technology for chip packaging and new materials is expected to change virtually all chip production.
“Industry continues to find new ways to innovate as Moore’s Law slows down”said Brett Simpson, a senior analyst at Arete Research. “The adoption of advanced packaging creates a new paradigm for the semiconductor industry, where chipmakers and foundries are clearly adding more value, and instead of selling silicon the industry will increasingly sell more complete platforms. We believe this is a critical development in computing at a time when large monolithic chips are no longer meeting customer needs. “
Last year, TSMC combined its wafer-level 3D IC platforms under an umbrella called 3DFabric, which includes frontend and backend technologies, as well as the latest TSMC offering, SoIC (integrated chip system) for silicon stacking. TSMC has several backend factories that assemble and test silicon arrays, including 3D stacks, in packaged devices. 3DFabric includes the company’s oldest CoWoS and InFO packaging technologies.
“Recent discussions at Semicon Taiwan and other events we have been able to attend have pointed to 3DFabric as a key piece in continuing to enable power, performance and system level improvements over the next decade as traditional scaling becomes more technically complicated and expensive ”.
Looking ahead to 2022, Wei said that SoIC will be ready for mass production and by the end of the same year the company will have a total of five dedicated factories for 3DFabric and yet despite advancing technology we are still in the TSMC does not have plans beyond 2 nm at the moment (which does not mean that, when they do, they will start planning to scale to smaller lithographs).