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The Intel, Samsung and TSMC CPU Nanometer Lie

The manufacturing processes of the chips that our hardware uses are usually expressed with a number followed by the term nanometers. But what does this term indicate today? Well, objectively nothing and that is why nanometers are a lie, since it has become a marketing term by all factories or foundries of processors. Whether we are talking about Intel, TSMC, Samsung and even the Chinese SMIC.

The lie of the nanometers today

Until the end of the 90s, it referred to the length of the logic gates used to build the different chips or semiconductors, but from the 250 nm node, a more aggressive position began to be taken regarding the length of the gates. logical is concerned. For example the 250nm node used logic gates with a length of 200nm instead of 250nm, and the trend was upward with the 180nm node the length used was 130nm.

That forced a change in the definition of what was the metric when defining a manufacturing node, which became the half-pitch, which for several generations coincided in length with the manufacturing node. But today they no longer match and nanometers have become a marketing term to inform us that a manufacturing node used by a factory or foundry to manufacture all kinds of semiconductors, or chips, is better than the previous one.

For example, TSMC’s so-called 20nm process has the same density as TSMC’s 16nm FinFet process, but the trade name of the latter case was used to talk about improvements by the use of FinFet transistors. We can also talk about the comparison between Intel’s 10nm node and TSMC’s 7nm.

How would lithographs scale in nanometers?

Nanometer evolution

Moore’s Law tells us that chips increase the density of their transistors every certain number of years, it must be taken into account that it was coined in the sixties where the manufacturing node corresponded to the length of the logic gates, which are distributed in matrix throughout the chip.

That is why reducing the length of each logic gate by 30% ends up reducing the size of a chip with the same internal organization in half. Decreasing the length of something by 30% means reducing it 0.7 times and 0.7two they are 0.49 times and hence doubling the density, since you are placing the same quality of transistors in half the area.

What does this have to do with the current situation? It is simple, for example the jump from a 16 nm FinFet process to a 7 nm one, if the classical measure is used, it would be an increase in density of four times, but instead it is promoted with twice the density. Which is further proof that when large foundries speak of a certain number of nanometers they are not mentioning a technical specification, but a marketing term.