With the advent of manufacturing technology Extreme Ultra Violet (EUV), the complexities of multi-pattern techniques developed in previous technology nodes can now be applied with the finest resolution that EUV provides. That, along with other more technical improvements, can lead to a decrease in the size of the transistors, allowing us to continue with the future of semiconductors and, now at last, we have reached the era of 2 nanometers.
The first chip at 2 nm is from IBM, how does it work?
Today’s announcement claims that IBM’s 2nm development will improve performance by 45% with the same power, or 75% efficiency with the same performance compared to modern 7nm chips. IBM would like to point out that it was the first institution to demonstrate 7nm in 2015 and 5nm in 2017, the latter of which was upgraded from FinFET to nanosheets technologies that allow further customization of the voltage characteristics of individual transistors.
IBM claims its process technology can place 50 billion transistors on a single chip the size of a fingernail (about 150 square millimeters), placing the density of transistors on this chip at 333 million transistors per square millimeter (MTr / mm2).
As you can see, the different functions have different official names with a variety of densities. It’s worth noting that these density numbers are often listed as peak densities, for transistor libraries where area is the primary matrix of concerns rather than frequency scaling; Often times, the fastest parts of a processor are half as dense as these numbers due to thermal and power issues.
Regarding the movement to the GAA / Nanosheet transistors, although IBM does not explicitly state this, the images show that this new processor at 2nm is using a three-stack GAA design. Samsung already uses GAA at 3nm, while TSMC is hoping to achieve its own 2nm for it. Rather, it is believed that Intel will somehow introduce it into its 5nm process.
IBM’s 3-stack GAA uses a cell height of about 75nm, a cell width of about 40nm, and individual nanofilts are 5nm high, separated from each other by 5nm. The polygonal pitch of the gate is 44 nm and the gate length is 12 nm. IBM says its design is the first to use lower dielectric isolation channels, allowing for the 12nm gate length, and that its internal spacers are a second-generation dry process design that helps enable development of these. nanosheets. This is complemented by the first use of the EUV pattern in the FEOL parts of the process, allowing EUV at all stages of the design.
Our readers may wonder why IBM is the first to have a 2nm chip and not Samsung or TSMC, which you hear the most about today. IBM continues to have one of the world’s leading research centers for semiconductor technology and, despite not having its own foundries, they develop their own products in collaboration with others. IBM sold its manufacturing facilities to GlobalFoundries With a 10-year partnership commitment in 2014, IBM is also currently working with Samsung itself and in fact recently announced a partnership with Intel.
No details have been provided on the first 2nm test chip, although at this stage it is likely nothing more than a simplified SRAM test circuit with electrical logic. The 12-inch wafer images show a variety of different light diffractions, likely pointing to a variety of test cases to assert the viability of the technology. IBM says the test design uses a multi-Vt scheme for high-performance, high-efficiency application demonstrations.
The chip has been designed and manufactured at IBM’s research facility in Albany, United States, where they have a clean room of no more and no less than 30,500 square meters. The purpose of this facility is to leverage IBM’s extensive portfolio of patents and licenses precisely to carry out collaborations with its partners.