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CPUs with big.LITTLE technology with TSMC 3nm

The development of the different processors is not something that is done overnight, while one is starting to be sold, the next is about to be mass-manufactured and the one from two generations on with its design already finished. This is why the Zen 5 rumors shouldn’t surprise us.

AMD to adopt big.LITTLE in Zen 5

At least that is what the rumors that have come out about the fifth generation Zen say, and that is AMD Zen 5 will use big LITTLE execution and therefore they will follow the same path that the ARM cores years ago and that Intel started the Lakefield, but that will massively standardize in Alder Lake.

The big LITTLE execution that the AMD Zen 5 is supposed to adopt is based on using two different types of cores for the CPU, fully compatible when executing the binary code but designed with two different performance metrics. Some are more focused on performance regardless of consumption, others would be more focused on consumption but at lower performance.

The composition of each CCD will continue to be 8 cores, with the corresponding IPC improvements and optimizations that AMD makes in the next two generations, but with each 8-core CCD each accompanied by 4 additional cores of less complexity. TAll manufactured in TSMC’s 3nm process, which at the moment has not been used for the manufacture of any mass processor, not even in PostPC devices.

We already had clues about it

AMD Zen 5 big.LITTLE patent

Specifically, an AMD patent that was published last year, which talks about a configuration of big LITTLE cores like the one that is rumored for the AMD Zen 5. The difference? It would not be a question of cores in different clusters, but they would share access to the L1 cache, which is the most private of the processors.

So the operation of the big LITTLE in Zen 5 could therefore be different from the ARM cores and even the Intel version and therefore the rumors about the AMD Zen 5 have been completely misinterpreted.

Return to the monolithic model in Zen 5?

Ryzen 4000 5000 6000 SoC

Another of the information that has been said is that the AMD Zen 5 will be APUs, which would partly mean that AMD in the face of Zen 5 will abandon the configuration in chiplets that I adopt in Zen 2 and that everything indicates that we will see in Zen 4 It’s too early to tell, but one of the weaknesses of AMD’s Zen architectures is latency due to the physical distance between the chiplet and the IOD. What’s more, AMD gives the Zen 2 and Zen 3-based SoCs less L3 cache to give their chiplet-based desktop CPUs a bit of an advantage.

The other possibility is that it is still based on chiplets, but that the IOD integrates an integrated GPU and its coprocessors, video codecs, display adapters, apart from the Northbridge and the Southbridge of the CPU. It is an idea that should not be discarded and it would be totally feasible to do so.

In any case, the only thing we can say is that it is still too early to talk specifically about Zen 5. More so when Zen 4 has not yet been presented and there is no commercial chip that uses this node in its manufacture.