There is no doubt that processors composed of chiplets will be the norm in the following years, we know that it will be the bet of future designs from both Intel, AMD and NVIDIA, in which each of them has developed a proprietary interface for communication for use with your architectures.
The Common Electrical Interface, on the other hand, is the interface that is being standardized for communication between the elements in a chiplet and that is not owned by these three companies. What’s more, many of the designs are built FPGA units that make use of this interface to communicate the different parts. Although before explaining what it consists of, it is best to take a tour through a series of basic concepts.
The concept of NoC
NoC or network on a chip, is the idea of making an intercommunication between the various components of the PC as if it were a network, for this each of the elements has a router that communicates it with the other elements, so only It is necessary that each element of the network has a built-in router that is used to communicate and communicate with the rest
Each element within the component network has its own address and the way to communicate between the different components is to make each element call the network address of another element, in which not only the processing elements have an address within the same, not only the processors and I / O interfaces, but also the memories that compose it, be it RAM, VRAM and even NVMe chips in order to facilitate communication.
The idea of an MCM like NoC
Something that differentiates a SoC from an MCM is that in the first case we have a central unit on the chip that is in charge of communicating with each other all the elements within the chip and these with the memory is common in all SoCs, regardless of which is whatever architecture we’re talking about, all SoCs contain that element in common.
But in an MCM composed of several separate elements, there must also be a unit that is in charge of communicating the different elements with each other. If we are talking about an SoC then there must be the same unit in charge of communication, but in the case that we are talking about a NoC in which each element can communicate with another directly then things already change.
In a NoC, communication is carried out between the different elements using a network interface, imagine this as a LAN network, but using much faster connections for communication between the different elements of the chiplet, due to the short distance and the material used.
What is the Common Electrical I / O?
The Common Electrical I / O shortened as CEI, is a series of agreements made by a consortium called Optical Internet working Forum (OIF), which is in charge of defining the common requirements for electrical interfaces with a communication speed with a transfer speed of 3.125, 6, 11, 25-28 and 56, 112 and soon 224 Gbps.
The CEI has been the basis for different types of I / O interfaces and protocols such as the Hyper Transport from which AMD’s Infinity Fabric derives, the SATA interface in various versions. various 803.3 and InfiniBand interfaces.
Its importance is due to the fact that while Intel and AMD are going to use their own proprietary interfaces to communicate the different chiplets within the MCM, the existence of a standard interface that can be used is extremely important not only in order to be able to deploy designs based on chiplets. by different processor designers, but also for the development of these.
The Common Electrical I / O is a SERDES-type interface, which in its current version can reach a transfer speed of 112 Gbps. It currently has different variants, but the ones that interest us are those related to chiplets, since they will be widely used for communication between the different elements.
A SERDES is a type of interface that what it does is take a series of data in parallel and transmit it in series to another, as it will do the opposite process, that is, it converts a serial signal into a parallel one again. Hence the SERDES dimension.
In the case of the current 112 Gbps interface, it uses a PAM4 type encoding, in such a way that it can reach 112 Gbps of speed using a 28 GHz clock speed for communication. Such clock speeds would be extremely counterproductive if we are talking about long distances, but it is not the case of an MCM composed of chiplets with an interposer below, in which the different elements are too close to communicate.
Within the Common Electrical I / O interface we have two types, on the one hand we have the one that is responsible for communication in a traditional chiplet, which in its 112 Gbps version is called CEI-112G-MCM and is designed to Wired with a distance between both ends of at most 2.5 mm, the short distance of the cable allows it to consume very little power per transfer.
The second type is designed for communication with an optical receiver, and yes, the next step after conventional interposers is to use optical interfaces for communication, although at the moment these are neither used nor will they be used in the short term in domestic systems.
Common Electrical I / O for external communication of chiplets
A chiplet, despite being made up of different units inside, can be seen as a single unit facing the outside and the way it communicates is through a series of I / O interfaces that provide connectivity.
Of course, for communication within the chiplet, this type of external interfaces need to be transformed into a signal of the Common Electrical I / O type, through a series of SERDES that are close to the periphery of the chip. just before the external interfaces, whether they were RAM, VRAM, PCI Express interfaces, etc.