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5 Bit PLC NAND FLASH, delayed by ARM controllers

The first forecasts and road maps were quite hopeful, where interestingly Intel and Toshiba were showing quite advanced with this new vertical packaging technology. The promises were many as we saw in their day, but now a giant like Western Digital arrives and throws water on the fire. Are there serious delays in the industry due to various complexities? Or is it a strategy to recover what was lost in the midst of rising prices and demand?

The viability of Flash PLCs in question, not before 2025?

As is often the case in an industry as volatile as NAND Flash, one statement can change everything and move the market. He was the head of strategy and technology for Western Digital at the Bank of America Merrill Lynch Global Technology Conference 2021 where he made the following statements:

I hope the transition [de QLC a PLC] slow down then maybe in the second half of this decade we’ll see some segments starting to get 5 bits per cell. We believe that QLC across the segment will occur in the next [generación BiCS 6] when most bits will be changed to QLC on the market. In the next two more years, we will see the rapid acceleration of QLC adoption.

And it is that the incremental gain is not so much when we go from 4 to 5 bits in the same cell, so only 25% more density is obtained. To get that gain, you are sacrificing a lot, you need additional redundancy, additional ECC, so the assumed net gain from loss of performance may not be as desirable.

As we already know, each jump in NAND Flash technology means a decrease in prices for the same capacity, since the size of the SSDs increases and the speeds, latencies and degradation are either maintained or improved. But the jump from TLC to QLC is far from that, at least for now, and although there are SSD models on the market with this technology, the reality and the average is that the resistance and performance have not been almost improved.

ECC error correction and ARM chip power

ARM processor

Apparently everything will revolve around a new ECC and the power of the chips that will include the new SSDs and not so much the technology itself. As we know, the chips in charge of the maintenance, performance and control algorithms of the SSDs with 64-bit ARM, the latest being the new R82. The numbers are really very good: + 2.25x fasterI ask and + 23% in general terms of multitasking improvement, all with up to 8 cores for an SSD.

What is the problem? Well, they are planned for 2023 or possibly 2024, so hopefully we would see the first high-end SSDs by the end of that year or the beginning of 2025. The delay and complexity is due to the complexity that PLC requires for error correction, where the current one would not be enough. 4KB LDPCThis requires more computing power, more redundant capacity and a better level of wear and tear on the drive, which has an impact on a chip as complex as it is powerful and hot.

So unless Intel and Toshiba figure it out, we talk about at least 2025 to see the first SSD PLCs on the market, which has prompted some comments about the coincidence that the industry is raising prices to compensate for losses and the end of said increase for the same year mentioned.